Integrated circuit and method for manufacturing an integrated circuit

ABSTRACT

Integrated circuit comprising a substrate carrying at least one transistor comprising an alternating grid ( 1 ) of source and drain regions (D, S) separated by a grid ( 14 ) of gate regions, e.g. a checkerboard pattern of source and drain regions. The source regions (S) are vertically connected to a first metal layer and the drain regions (D) are vertically connected to a second metal layer. At least one of the first metal layer and the second metal layer comprises a metal grid ( 30, 40 ) of a plurality of interconnected metal portions ( 32, 42 ) arranged such that said grid comprises a plurality of gaps ( 34, 44 ) for connecting respective substrate portions to a further metal layer. Method for manufacturing such an integrated circuit.

FIELD OF THE INVENTION

The present invention relates to an integrated circuit (IC) having atleast one transistor, said transistor comprising a grid of unit cellsincluding source and drain regions separated by a grid of gate regions.

The present invention further related to manufacturing such an IC.

BACKGROUND OF THE INVENTION

The downscaling of the dimensions of ICs such as CMOS ICs continuallyposes IC designers with difficult design challenges, not in the leastbecause the reduction in feature size is usually accompanied by a demandfor the integration of a higher number of components in the IC.Typically, this makes it increasingly difficult to ensure that allsemiconductor components of the IC can be properly connected to themetal layers of the IC. In addition, the reduction of the feature sizeof a building block of the IC such as a transistor must be achievedwhilst ensuring that the performance of the transistor or at least theoverall performance of the IC is not adversely affected. It will beobvious that the above challenges are by no means trivial.

For instance, it is difficult to achieve a compact power transistor,since such a transistor typically has to provide a high power output,for which a low-resistive channel is required. This may be achieved byincreasing the dimensions of the channel and by placing strips of thesource (S), drain (D) and channel (C) regions in parallel in aninterdigited fashion, e.g. SCDCSCDC . . . . However, such a layout isnot particularly area-efficient and requires interdigited metalstructures for connecting these transistor regions, which cannot beautomatically routed due to their complexity, thus adding to thecomplexity and cost of the design.

An improved layout is disclosed in US 2006/0238241. This patentapplication discloses a QVDMOS transistor comprising a checkerboardpattern of source and drain regions, wherein the source and drainregions are separated from each other by a grid of gate regions. Thisimproves the effective channel width of the transistor, but complicatesthe interconnection of the transistor regions to the metal layers of theIC, as indicated in US 2006/0238241. Moreover, a further problem is thatthe area-efficient checkerboard layout of the source and drain regionsmakes it more difficult to provide additional contacts to the substrate.This is particularly relevant in CMOS technology where contacts to thesubstrate are required to prevent latch-up. Additional contacts may beprovided in the periphery of the transistor but this has thedisadvantage that a relatively large number of contacts is required toprovide satisfactory protection against latch-up, thereby off-settingthe area gains achieved by the checkerboard layout.

SUMMARY OF THE INVENTION

The present invention seeks to provide an IC that overcomes at leastsome of the aforementioned problems.

The present invention further seeks to provide a method of manufacturingsuch an IC.

According to an aspect of the present invention, there is provided an ICcomprising a substrate carrying at least one transistor comprising analternating grid of source and drain regions separated by a grid of gateregions, wherein the respective source regions are vertically connectedto a first metal layer and the respective drain regions are verticallyconnected to a second metal layer, at least one of the first metal layerand the second metal layer comprising a metal grid having a plurality ofpartially interconnected metal portions arranged such that said metalgrid comprises a plurality of gaps for connecting respective substrateportions to a further metal layer.

Such an IC has the advantage that the higher metal layers can beconnected to lower metal layers or structures in the substrate throughthe periodic gaps between the partially overlapping rectangular metalportions, which facilitates the interconnection of the alternatingsource and drain regions. In the context of the present invention, theterm substrate may refer to a common chip substrate, an epitaxial layeron top of the common chip substrate or a local p-well embedded in ann-well, e.g. a triple well technology.

In a preferred embodiment, the alternating grid comprises a plurality ofunit cells, each unit cell comprising a grid of N building blocks, Nbeing an integer having a value of at least four, said N building blockscomprising a single substrate contact and (N−1) source and drainregions, the source and drain regions of the unit cells being separatedby at least a part of the grid of gate regions.

In such an IC, the connections to the substrate are included in thecheckerboard pattern defined by the building blocks of the unit cellssuch that no additional substrate contacts in the periphery of thetransistor layout are required. This has the further advantage thatfewer contacts are required because the regularity of the substratecontacts in the grid provides a more efficient way of connecting thesubstrate. Hence, in case of a CMOS IC, a very efficient latch-upprotection may be provided by the substrate contacts in the unit cells.To this end, the size of the unit cell, i.e. the value of N, may bechosen in accordance with the required number of substrate contacts toprovide effective latch-up protection. The number of substrate contactsmay be determined using appropriate simulation models and/orexperimental data. This way, the number of substrate contacts may bekept to the minimum number of contacts required, thus reducing the areaoverhead and cost of the IC.

It will however be appreciated that the present invention is not limitedto CMOS ICs and that the substrate contacts may be used for otherpurposes than latch-up protection, such as for the provision of a backbias to a particular part of the substrate.

In an embodiment, there is a difference of one between the total numberof source regions and the total number of drain regions per unit cell.For instance, each unit cell may comprise (N/2) source regions and(N/2−1) drain regions. This provides the most area-efficient layout forthe transistor in terms of performance and effective gate width.

In case of a CMOS IC, the substrate contact may provide a direct contactto the p-type substrate for an nMOS transistor. Alternatively, thesubstrate may comprise a plurality of n-wells, wherein the substratecontact of each unit cell is connected to one of said n-wells. Thiswould provide a latch-up protection arrangement for pMOS transistor.

Preferably, at least one of the first metal layer and the second metallayer comprises a plurality of partially overlapping rectangular metalportions arranged such that said metal layer comprises a plurality ofgaps for connecting the substrate contacts to a further metal layer. Theprovision of periodic gaps or openings in the metal grid(s) facilitatesthe connection of the substrate contacts to higher metal layers in astraightforward manner, thus reducing the cost of manufacturing the IC.

In an embodiment, each rectangular metal portion has an area and shapesubstantially similar to a corresponding source or drain region. Thismeans that the first metal grid and the second metal grid can be stackedon top of each other with the rectangular portions of the upper metalgrid connecting to the corresponding regions in the substrate throughthe gaps in the lower of the two metal grids. It is pointed out that inthe context of the present invention, the phrase ‘rectangular’ includessquare shapes.

The use of the metal grids of the present invention further facilitatesthe connection of these grids to the highest metal layers of the IC,which are typically low-ohmic, for instance to provide a good conductiveexternal connection. In particular, the IC may comprise a firstlow-ohmic metal layer conductively coupled to the first metal gridthrough at least one stacked via, and/or a second low-ohmic metal layerconductively coupled to the second metal grid through at least onestacked via. This is an important advantage, because in contrast toprior art ICs using strip-based interconnects, which could not beconnected using stacked vias because the via size would be too large toallow connection to the small sized metal strips, the rectangularportions provide a sufficiently large area for receiving such a stackedvia.

The present invention is particularly advantageous when the at least onetransistor is a power transistor, because the dimensions of a powertransistor are typically governed by the power requirements of thetransistor (this is less the case for transistors in e.g. digital logiccircuits). Hence, the size of a power transistor can be significantlyreduced by the transistor layout of the present invention.

The IC of the present invention may be integrated in an electronicdevice, such as linear (class AB) audio power amplifiers, switching(class D) audio power amplifiers, linear voltage regulators, switchingvoltage (power) converters, HF and RF amplifiers, and line drivers forbuses and cables. It is particularly advantageous if the electronicdevice itself is small, e.g. a hand-held device such as a mobilecommunications device, because the size reduction achieved in the IC ofthe present invention frees valuable additional real estate for theelectronic device to be used for other functionality. More importantly,the size reduction facilitates the manufacture of a reduced cost ICbecause the cost of an IC scales with its area, thus reducing the costof the electronic device including the IC. This is an importantadvantage because competition in the consumer electronics market ishigh, such that manufacturing cost reduction play an important part isimproving a market position.

According to another aspect of the present invention, there is provideda method of manufacturing integrated circuit comprising at least onetransistor formed on a substrate, said method comprising providing asubstrate carrying at least one transistor comprising an alternatinggrid of source and drain regions separated by a grid of gate regions,providing a first metal layer such that the respective source regionsare vertically connected to the first metal layer; providing a secondmetal grid such that the respective drain regions are verticallyconnected to the second metal layer, wherein at least one of the firstmetal layer and the second metal layer comprises a metal grid having aplurality of interconnected metal portions arranged such that said metalgrid comprises a plurality of gaps for connecting respective substrateportions to a further metal layer.

The provision of at least one metal grid comprising such a plurality ofpartially overlapping rectangular metal portions facilitates theformation of metal to metal or metal to substrate interconnections, aspreviously explained.

In a preferred embodiment, the step of providing the substrate comprisesproviding a grid of unit cells on said substrate, each unit cellcomprising a grid of N building blocks, N being an integer having avalue of at least four, said N building blocks comprising a singlesubstrate contact and (N−1) source and drain regions, the source anddrain regions of the unit cells being separated by at least a part ofthe grid of gate regions. This provides an IC having a reducedfootprint, as previously explained.

BRIEF DESCRIPTION OF THE EMBODIMENTS

Embodiments of the invention are described in more detail and by way ofnon-limiting examples with reference to the accompanying drawings,wherein

FIG. 1 schematically depicts an embodiment of a transistor layout of theIC of the present invention;

FIG. 2 schematically depicts the current flows in the transistor layoutof FIG. 1;

FIG. 3 schematically depicts a metal grid for interconnecting the sourceregions of the transistor layout of FIG. 1;

FIG. 4 schematically depicts a metal grid for interconnecting the drainregions of the transistor layout of FIG. 1;

FIG. 5 shows a layout of an IC design using strip-based power CMOStransistors; and

FIG. 6 shows a layout of an IC design using CMOS power transistorshaving the transistor layout of FIG. 1.

DETAILED DESCRIPTION OF THE DRAWINGS

It should be understood that the Figures are merely schematic and arenot drawn to scale. It should also be understood that the same referencenumerals are used throughout the Figures to indicate the same or similarparts.

FIG. 1 depicts a layout of a transistor such as a power-MOS transistorin accordance with an embodiment of the present invention. In thislayout, the source regions labeled S and the drain regions labeled D arelaid out in a grid 1 such as a checkerboard pattern, with the sourceregions S and the drain regions D being separated by a grid of gateregions 14. The source, drain and gate regions may be formed in anysuitable manner. For instance, the gate regions may be polysilicon gateregions, and may be insulated from the underlying channel region bymeans of an insulating material such as SiO₂ or a high-k dielectricmaterial, which is a material having a higher dielectric constant thanSiO₂.

The grid 1 is divided into a number of unit cells 10, which eachcomprise a number of N building blocks, wherein N is a positive integerhaving a value of at least four. The N building blocks comprise N−1source and drain regions as well as a substrate contact 12 such thateach unit cell facilitates the connection of a metal layer of the ICincorporating the grid 1. Such a substrate contact 12 is intended to beused to provide latch-up protection to the transistor but may also beused for other purposes, such as to provide a (back-) bias to thesubstrate. In case of a CMOS transistor, the substrate contact 12 willbe located in the substrate of an nMOS (power) transistor, and will belocated in the n-well of a pMOS (power) transistor to facilitate thenecessary latch-up protection.

The size of unit cell is typically based on the number of substratecontacts 12 required to implement the desired functionality providedthrough these contacts. For instance, in case of latch-up protection fora power transistor in NXP's CMOS75 technology, which is a 0.35 microntwin-well 3.3 V CMOS technology, N has been calculated to be sixteen.However, for different technologies, e.g. different CMOS technologies,the value of N may be different. This may also depend on thefunctionality to be provided through the substrate contacts 12.

In FIG. 1, the unit cells 10 and the grid 1 are shown to have a squarelayout. This is by way of non-limiting example only. The unit cells 10generally have dimensions of H*V=N wherein H is the number of buildingblocks in a horizontal direction and V is the number of building blocksin a vertical direction. H and V may have the same value, yielding asquare building block 10 or different values, yielding a rectangularbuilding block 10. Similarly, the grid 1 may also adopt a differentshape, such as a rectangular shape or even a non-rectangular shape suchas an L-shape or a U-shape for instance. Hence, the transistor layout ofthe present invention makes it possible to more effectively use theavailable silicon real estate, especially when the available real estatehas an awkward, i.e. non-rectangular shape.

It will be appreciated that because the substrate can be contacted usingvertical contacts, the number of contacts required to provide thesubstrate with effective latch-up protection can be reduced, therebyreducing the footprint of the transistor including its interconnectstructures. This is particularly advantageous for transistors that haveto handle large currents such as currents of 1 Ampere or more, i.e.power transistors, because such transistors require a very large gateeffective width, e.g. in excess of 10⁴ micron, and consequently have afootprint that is several orders in magnitude larger than a digitallogic transistor, such that large gains in the overall area of an IC canbe achieved if the footprint of such a power transistor can be reduced.Such power transistors may for instance be used in audio poweramplifiers, voltage regulators, voltage converters, RF amplifiers, busline drivers and so on.

In FIG. 1, each unit cell 10 has its own grid of gate regions 14, withthe respective gate grids being interconnected via bridging gatestructures 16. In other words, the gate regions have been omitted aroundthe substrate contacts 12. However, this gate grid arrangement is shownby way of non-limiting example only. Other arrangements, such as asingle gate grid 14 for the checkerboard grid 1, in which the substratecontacts 12 are also surrounded by gate structures, may also becontemplated.

As is known from the prior art, a transistor layout based on analternating grid of source and drain regions provides an area-efficientway of providing a transistor with a large effective channel width. Thisis because such an alternating grid comprises many parallel channels.This is demonstrated in FIG. 2, which shows a unit cell 10 of the grid 1in more detail. The gate structure grid 14 defines where a current canflow between a drain region D and a source region S, as indicated by thearrows in FIG. 2.

A solid arrow identifies a current flow (or channel) inside the unitcell 10 whereas a dashed arrow identifies a current flow (or channel)shared between two neighboring unit cells 10. The unit cell 10 in FIG. 2has an effective channel width of 28 units compared to 16 units for aprior art one-dimensional transistor based on parallel interdigiteddrain and source strips. The effective channel width may be obtained bycounting the solid arrows as a single channel width unit and a dashedarrow as half channel width unit because it is shared with another unitcell. This clearly demonstrates the improvement in channel width perunit area for the checkerboard layout of FIG. 2. The unit cell 10 inFIG. 2 is surrounded by further unit cells 10 on all four edges.Obviously, for a unit cell 10 at the edge of the grid 1, the effectivechannel width will be slightly lower because not all four edges of theunit cell 10 have a channel extending to another unit cell.

A particularly advantageous aspect of the present invention isdemonstrated in FIG. 3, in which an interconnect metal layer isdepicted. The metal layer is the interconnect layer for the sourceregions S of the transistor layout of FIG. 1, as demonstrated in FIG. 3by the dashed regions S under the metal portions 32. The actualinterconnection between the dashed regions S and the metal portions 32may be made in any suitable manner, e.g. using vias through one or moreinsulating layers (not shown) between the metal layer and the substrate.Since the design and formation of such interconnections is routinepractice for the person skilled in the art, this will not be furtherexplained for reasons of brevity only. The portions 32 may have the sameshape as the underlying source regions, but may be larger in area thanthe source regions. The increase in area may facilitate a larger overlapbetween the respective metal portions 32 to reduce the resistance of themetal grid 30.

A key feature of the metal layer is that it is formed of interconnectedmetal portions such that a metal grid 30 is formed, which, due to thefact that the metal portions 32 are only partially interconnected,provides gaps 34 in between the metal portions 32 that facilitateunderlying substrate structures to be connected through the metal grid30. Preferably, the partial interconnections are realized by designingthe metal grid 30 such that the shapes of the individual metal portions32 partially overlap. It will be appreciated that this is not an overlapin the physical sense but an overlap in geometrical sense where multipleshapes are merged into a single shape (the metal grid 30) by such apartial overlap.

For instance, vias 36 may be provided in the gaps 32 over the drainregions D to connect the drain regions to a higher metal layer, and vias38 may be provided to connect the substrate contacts 12 to a highermetal layer. Due to the overlap between the metal portions 32, the metalgrid 30 still acts as a metal layer. The amount of overlap between themetal portions 32 may be varied based on the ohmic requirements of themetal grid 30.

The grid 30 of the present invention may be realized in any suitableconductive material, such as Al, Cu, salicided polysilicon or any othermetal or metal alloy available in the technology of interest. In thecontext of the present invention, the phrase ‘metal’ is to include metalalloys and other conductive materials that show similar conductivitycharacteristics, e.g. salicided polysilicon.

A further advantage of the metal portions 32 compared to the metalstrips used in the prior art interdigited power transistors is that thefoot print of the metal portions 32 is sufficiently large to support theformation of vias such as stacked vias to higher metal layers thereon.This overcomes interconnection problems in the prior art one-dimensionalinterdigited transistors, where the metal strips over the interdigitedsource and drain regions were too small to allow the interconnection ofthese strips to higher metal layers using the relatively bulky stackedvias.

The formation of such stacked vias may be facilitated by the use of asecond metal grid 40 for interconnecting the drain regions D, as shownin FIG. 4. The partially overlapping metal portions 42 are located overthe drain regions D such that they can be connected to the drain regionsthrough the gaps 34 in the first metal grid 30. The gaps 44 between themetal portions 42 in the second metal grid 40 are located over the metalportions 32 of the first metal grid 30 and can be used to interconnectthese metal portions 32 to higher metal layers, e.g. using stacked vias46. In the second metal grid 40, the metal portions 42 located over thesubstrate contacts 12 are omitted such that the substrate contacts 12can be connected to a higher metal layer via the gaps 34 in the firstmetal grid 30 and the gaps provided by the omission of the metalportions 42 in the second metal grid 40.

The metal grids 30 and 40 may be considered to provide powerinterconnect planes to the underlying source and drain regions. Suchplanes are characterized by a much lower interconnect resistance thanthe prior art metal strip arrangements of the interdigited powertransistors, thus providing a substantial improvement in powerconsumption compared to these prior art devices.

In FIGS. 3 and 4, the metal grids 30 and 40 are composed of partiallyoverlapping square metal portions 32 and 42 respectively. It is howeveremphasized that the metal portions 32 and 42 have been shown as squaremetal portions by way of non-limiting example only. Other shapes, suchas rectangular shapes or even non-rectangular shapes may also becontemplated to form the metal grids 30 and 40, as long as the gaps 34and 44 can be provided using these alternative shapes for the metalportions 32 and 42.

It will be appreciated that the stacking order of the metal grids 30 and40 in the IC of the present invention may be reversed without departingfrom the teachings of the present invention; instead of the first metalgrid 30 for interconnecting the source regions S being located betweenthe IC substrate and the second metal grid 40 for interconnecting thedrain regions D, the second metal grid 40 may be located between thefirst metal grid 30 and the IC substrate. Moreover, it will beappreciated that the higher of the two metal layers may a conventionalmetal layer if the lower metal grid such as metal grid 30 in thediscussed example does not require interconnection to a higher metallayer by means of vias such as stacked vias.

For the sake of clarity, it is pointed out that in the context of thepresent invention, ‘lower’ is intended to refer to a layer or gridcloser to the substrate, i.e. the bottom of the IC, when considering thestack of layers forming the IC, and ‘higher’ is intended to refer to alayer or grid closer to the top of the IC when considering the stack oflayers forming the IC.

It is further emphasized that the metal grids 30 and/or 40 may also beused in combination with alternating grids of source and drain regionsonly, in which the substrate contacts 12 are omitted. In this case, thesecond metal grid 40 will further comprise overlapping metal portions 42in the areas of the metal grid 40 located over the substrate contacts 12in FIG. 4. Although the benefit of the reduced number of substratecontacts required to provide effective latch-up protection is sacrificedin such a checkerboard-type arrangement of source and drain regions,such an IC still benefits from the fact that the interconnection of thesource and drain regions in such an alternating grid can be more easilyachieved, as previously discussed.

It will be appreciated that if one of the source or draininterconnection metal layers is the top metal layer in the metal layerstack of the IC of the present invention, there is no need for thismetal layer to be shaped in the form of a metal grid 30 or 40 becausesuch a metal layer does not have to facilitate connections of lowerstructures to a higher metal layer. In such a case, the relevant metallayer may be a continuous metal layer or another suitable metal layerknown in the art.

It is further pointed out that the specific embodiment of the top metallayer of the IC of the present invention is not essential to thisinvention. Any suitable implementation of the top metal layer may bechosen. For instance, the top metal layer may carry a bumpinterconnection layer for connecting the top metal layer to e.g. anotherchip, a package or a component board. Alternatively, such a bumpinterconnection layer may also be provided in parallel with the topmetal layer to reduce the resistance of the power plane. Many othersuitable embodiments will be apparent to the skilled person.

FIG. 5 depicts an IC layout of a class-D stereo audio amplifiercomprising a digital signal processing portion 52, analog circuitry 54and prior art power MOS transistors 50 in an interdigited strip layout.FIG. 6 depicts an IC layout of the same class-D stereo audio amplifierin which the interdigited power MOS transistors 50 have been replacedwith power MOS transistors 60 according to an embodiment of the presentinvention. It is clearly demonstrated that the power MOS transistors 60according to an embodiment of the present invention provides a footprintreduction of almost 50% compared to the prior art power MOS transistors50 in an interdigited strip layout.

It should be noted that the above-mentioned embodiments illustraterather than limit the invention, and that those skilled in the art willbe able to design many alternative embodiments without departing fromthe scope of the appended claims. In the claims, any reference signsplaced between parentheses shall not be construed as limiting the claim.The word “comprising” does not exclude the presence of elements or stepsother than those listed in a claim. The word “a” or “an” preceding anelement does not exclude the presence of a plurality of such elements.The invention can be implemented by means of hardware comprising severaldistinct elements. In the device claim enumerating several means,several of these means can be embodied by one and the same item ofhardware. The mere fact that certain measures are recited in mutuallydifferent dependent claims does not indicate that a combination of thesemeasures cannot be used to advantage.

1. An integrated circuit comprising a substrate carrying at least onetransistor comprising an alternating grid of source and drain regionsseparated by a grid of gate regions, wherein the respective sourceregions are vertically connected to a first metal layer and therespective drain regions are vertically connected to a second metallayer, at least one of the first metal layer and the second metal layercomprising a metal grid of a plurality of interconnected metal portionsarranged such that said grid comprises a plurality of gaps forconnecting respective substrate portions to a further metal layer.
 2. Anintegrated circuit according to claim 1, wherein the grid comprises aplurality of unit cells, each unit cell comprising a grid of N buildingblocks, N being an integer having a value of at least four, said Nbuilding blocks comprising a single substrate contact and source anddrain regions, the source and drain regions of the unit cells beingseparated by at least a part of the grid of gate regions.
 3. Anintegrated circuit according to claim 2, wherein each unit cellcomprises source regions and drain regions.
 4. An integrated circuitaccording to claim 2, wherein the substrate comprises a plurality ofn-wells, and wherein the substrate contact of each unit cell isconnected to one of said n-wells.
 5. An integrated circuit according toclaim 2, wherein each unit cell comprises a grid of gate regions, thegate region grids of the respective unit cells being interconnected. 6.An integrated circuit according to claim 1, wherein the first metallayer comprises the plurality of interconnected metal portions, andwherein the drain regions are connected to the second metal layerthrough the gaps in the first metal layer.
 7. An integrated circuitaccording to claim 1, wherein each metal portion has a shape that issubstantially similar to a corresponding source or drain region and anarea that is larger than the area of the corresponding source or drainregion.
 8. An integrated circuit according to claim 1, furthercomprising a first low-ohmic metal layer conductively coupled to thefirst metal layer through at least one stacked via.
 9. An integratedcircuit according to claim 1, further comprising a second low-ohmicmetal layer conductively coupled to the second metal layer through atleast one stacked via.
 10. An integrated circuit according to claim 1,wherein the at least one transistor is a CMOS transistor.
 11. Anintegrated circuit according to claim 1, wherein the at least onetransistor is a power transistor.
 12. An electronic device comprising anintegrate circuit according to claim
 1. 13. A method of manufacturingintegrated circuit comprising at least one transistor formed on asubstrate, said method comprising: providing a substrate carrying atleast one transistor comprising a grid of source and drain regionsseparated by a grid of gate regions, providing a first metal layer suchthat the respective source regions are vertically connected to the firstmetal layer; and providing a second metal layer such that the respectivedrain regions are vertically connected to the second metal layer,wherein at least one of the first metal layer and the second metal layercomprises a metal grid comprising a plurality of interconnected metalportions arranged such that said metal grid comprises a plurality ofgaps for connecting respective substrate portions to a further metallayer.
 14. A method according to claim 13, wherein the step of providinga substrate comprises providing a plurality of unit cells, each unitcell comprising a grid of N building blocks, N being an integer having avalue of at least four, said N building blocks comprising a singlesubstrate contact and source and drain regions, the source and drainregions of the unit cells being separated by at least a part of the gridof gate regions.
 15. A method according to claim 13, wherein the firstmetal layer comprises the plurality of partially overlapping metalportions and wherein the first metal layer is located between thesubstrate and the second metal layer, the method further comprising thestep of connecting the drain regions to the second metal layer throughthe gaps in the first metal layer.